This application is related to Japanese application No. HEI 11(1999) filed on August 2nd, whose priority is claimed under 35 USC xc2xa7119, the disclosure of which is incorporated by reference in its entirety.
1. Field of the Invention
The present invention relates to a process for manufacturing a semiconductor memory device. More particularly, it relates to a process for manufacturing a semiconductor memory device having floating gates and control gates in which insulating films are provided between the floating gates.
2. Description of Related Art
In the field of semiconductor memory devices having floating gates and control gates, a technique for increasing a coupling ratio [C2/(C1+C2), C1: a coupling capacitance between a floating gate and a semiconductor substrate, C2: a coupling capacitance between a floating gate and a control gate] has been proposed with the intension of reducing voltage, for example, by Japanese Unexamined Patent Publication No. HEI 9-102554.
Hereinafter, a process for manufacturing a semiconductor memory device based on this technique will be explained. FIGS. 14(a) to 14(g) are sectional views taken along the line X-Xxe2x80x2 in FIG. 13(a) and FIGS. 14(axe2x80x2) to 14(gxe2x80x2) are sectional views taken along the line Y-Yxe2x80x2 in FIG. 13(a).
First, as shown in FIGS. 14(a) and 14(axe2x80x2), a tunnel oxide film 22 of about 10 nm thick is formed on an active region of a p-type semiconductor substrate 21 by thermal oxidization. Then, a phosphorus-doped polysilicon film 23 of 100 to 200 nm thick is formed thereon as a material for a lower floating gate. A resist film is formed thereon and patterned by photolithography to form a resist pattern R1 (see FIG. 13(b)). Using the resist pattern R1 as a mask, the polysilicon film 23 and the tunnel oxide film 22 are sequentially etched into a floating gate by reactive ion etching (RIE) method.
Next, as shown in FIGS. 14(b) and 14(bxe2x80x2), using the resist pattern R1 and the polysilicon film 23 as a mask, arsenic ions, for example, are implanted at an angle inclined by 7xc2x0 from a normal line with respect to the substrate surface (hereinafter abbreviated as xe2x80x9cat 7xc2x0xe2x80x9d) at an implantation energy of 70 keV in a dose of 1xc3x971015/cm2 to form a high concentration impurity layer 29.
As shown in FIGS. 14(c) and 14(cxe2x80x2), the resist pattern R1 is removed and then phosphorus ions, for example, are implanted along the direction perpendicular to the substrate surface (hereinafter abbreviated as xe2x80x9cat 0xc2x0xe2x80x9d) at an implantation energy of 50 keV in a dose of 3xc3x971013/cm2 using the polysilicon film 23 as a mask to form a low concentration impurity layer 28.
Then, as shown in FIGS. 14(d) and 14 (dxe2x80x2), the resulting semiconductor substrate 21 is heated at 900xc2x0 C. for 10 minutes under nitrogen atmosphere to form impurity layers 28a and 29a in which impurities are activated.
As shown in FIGS. 14(e) and 14(exe2x80x2), a silicon oxide film of about 200 to 300 nm thick is formed on the entire surface of the semiconductor substrate 21 by chemical vapor deposition (CVD) method and etched back by RIE method until the polysilicon film 23 is exposed to form a buried insulating film 30 in a space between the floating gates. At this time, the buried insulating film 30 is arranged so that sidewalls of the polysilicon film 23 are partially exposed.
Then, as shown in FIGS. 14(f) and 14(fxe2x80x2), for increasing the gate coupling ratio, a phosphorus-doped polysilicon film of about 100 nm thick is formed on the entire surface of the semiconductor substrate 21 and etched back by RIE method to form a polysilicon film 31 which will be a projection of the floating gate.
Next, as shown in FIGS. 14(g) and 14(gxe2x80x2), a silicon oxide film of 6 nm thick by thermal oxidation, a silicon nitride film of 8 nm thick by CVD method and a silicon oxide film of 6 nm thick by CVD method are deposited in this order on the semiconductor substrate 21 to form an ONO film 32 as a dielectric film between the floating gate and the control gate. Further, a phosphorus-doped polysilicon film of 100 nm thick and a tungsten silicide film of 100 nm thick are sequentially formed thereon to provide a polyside film of 200 nm thick. A resist film is formed thereon and patterned into a resist pattern R3 by photolithography (see FIG. 13(b)). Using the resist pattern R3 as a mask, the polyside film, the ONO film 32, the polysilicon film 31 and the polysilicon film 23 are etched successively by RIE method to form a control gate 33 and floating gates 23a and 31a. 
The resist pattern R3 is removed and then boron ions, for example, are implanted at 0xc2x0, 10 to 40 keV and 5xc3x971012 to 5xc3x971013/cm2 using the control gate 33 as a mask to form an impurity layer 34 for memory device isolation.
Thereafter, interlayer insulating film, contact hole and metal wiring are formed by a known technique to complete a semiconductor memory device.
FIG. 15 shows an equivalent circuit diagram of a semiconductor memory device having asymmetric source/drain regions in which a coupling ratio C2/C1 is increased as described above.
In FIG. 15, Tr.00 to Tr.32 indicate memory cells each having a floating gate, WL 0 to 3 indicate word lines connected to the control gates of the memory cells and BL 0 to 3 are bit lines connected to the common source/drain diffused wiring layers of the memory cells. The word line WL 0 is connected to the control gates of Tr.00, Tr.01 and Tr.02, and the word line WL 1 is connected to the control gates of Tr.10, Tr.11 and Tr.12, respectively. The bit line BL 1 is connected to the drains of Tr.01, Tr.11, Tr.21 and Tr.31 or the sources of Tr.00, Tr.10, Tr.20 and Tr.30. The bit line BL 2 is connected to the drains of Tr.02, Tr.12, Tr.22 and Tr.32 or the sources of Tr.01, Tr.11, Tr.21 and Tr.31.
Table 1 shows operating voltages at reading, writing and erasing in Tr.11 of FIG. 15. Further, FIG. 16 shows a state where information is read from the selected memory cell Tr.11, FIG. 17 a state where information is written in Tr.11 and FIG. 18 a state where information is erased from Tr.10 to Tr.12 connected to the word line WL 1 including Tr.11.
Writing in the memory cell is defined as Vth less than 2V and erasing is defined as Vth greater than 4V.
As shown in FIG. 16 and Table 1, information of the memory cell is read by applying a voltage of 3V to the control gate, grounding the substrate and the drain, and applying a voltage of 1V to the source so as to pass current i.
As shown in FIG. 17 and Table 1, information is written in Tr.11 by applying xe2x88x9212V to the control gate, grounding the substrate and applying 4V to the drain so that electrons are drawn from the floating gate utilizing a FN tunneling current flowing through a thin oxide film in a region where the drain and the floating gate are overlapped. At this time, a voltage of 4V applied to the drain is also applied to the source of Tr.10 sharing the common diffused wiring layer with the drain of Tr.11. However, a depletion layer is formed within the substrate because the impurity concentration in the source is low and an electric field actually applied to the thin oxide film in the overlapped region of the source and the floating gate is not sufficient to generate the FN tunneling current. As a result, information is selectively written only in the memory cell including the floating gate overlapped with the drain (high concentration impurity layer).
As shown in FIG. 18 and Table 1, information is erased from Tr.11 by applying 12V to the control gate, and xe2x88x928V to the source/drain and the substrate so that electrons are injected into the floating gate utilizing the FN tunneling current flowing through the entire channel. At this time, the same voltage is applied to the substrate, the control gates and the sources/drains of Tr.10 and Tr.12 connected with Tr.11 through the word line WL 1, so that data of the memory cells connected to the selected word line are erased at the same time.
As shown in FIGS. 14(g) and 14(gxe2x80x2), at the patterning of the polysilicon films 23 and 31 into the floating gates 23a and 31a, and the polyside film into the control gate 13, the buried insulating film 30 is exposed when the polyside film, the ONO film 32 and the polysilicon film 31 are removed by etching method. Accordingly, the buried insulating film 30 serves as a protective film against the etching. Further, on the surface of the buried insulating film 30, a reaction product 35 is generated which ensures a high selective etching rate of the polysilicon and functions as a protection of the surface of the buried insulating film 30.
As the polysilicon film 23 is further etched, a portion 23b of the polysilicon film 23 remains on vertical sidewalls of the buried insulating film 30 in a fence-like form slightly lower than the height of the buried insulating film 30 as shown in FIG. 19(a). This is because the reaction product 35 generated on the surface of the buried insulating film 30 extends to or covers the polysilicon film on the sides of the buried insulating film 30 so that the etching of the polysilicon film 23b on the sidewalls of the buried insulating film 30 is locally slowed.
The thus remained polysilicon film 23b causes a short circuit of the floating gate which is supposed to be isolated at the patterning of the control gate. This leads to a failure of the semiconductor memory device.
Where the polysilicon film 23 is etched at a high selective rate with respect to the buried insulating film 30 as in the above-described case, the height of the buried insulating film 30 should be about 50 nm or less so as not to leave the polysilicon film 23b in the fence-like form.
On the other hand, where the polysilicon film is etched at a low selective rate with respect to the buried insulating film 30, generation of the reaction product on the surface of the buried insulating film 30 is inhibited. Accordingly, the buried insulating film 30 is reduced in height while etching the polysilicon film 23. Only when the height is 50 nm or less, remaining of the polysilicon film 23b in the fence-like form is avoided.
However, where the polysilicon film is etched at a low selective rate as mentioned above, it is hard to control the height of the buried insulating film 30 to be 50 nm or less when the etching of the polysilicon film is finished. That is, it is extremely difficult to control the thickness of the buried insulating film 30 in consideration of variation in forming the buried insulating film 30, variation in etching back the buried insulating film 30 and variation in film reduction of the buried insulating film while etching the polysilicon film.
Further, in terms of variation in a film which will be formed thereon in a later step such as a control gate 33, it is essential to use a polysilicon film having a high selective etching rate with respect to the buried insulating film 30 to compensate the variations.
Accordingly, a conductive film having a high selective etching rate with respect to an insulating film is required as well as the insulating film contacting the sides of the polysilicon film needs to be thinned.
Moreover, when the control gate 33 is patterned, the polysilicon film for the control gate, the ONO film 32 and the polysilicon film for the floating gate are etched in this order. Therefore an etching protective film having enough thickness in view of the thickness of the ONO film 32 to be etched is required. That is, the buried insulating film 30 which serves as the etching protective film and is filled in the space between the polysilicon films needs to be formed thicker than the total thickness of the floating gate and the ONO film.
However, this is inconsistent with the need of the thin buried insulating film described above, which makes the formation of the control gate 33 difficult.
Further, for etching back the polysilicon film into a projection of the floating gate to increase the coupling ratio, the width of the space between the floating gates needs to be about three times greater than the thickness of the polysilicon film. Otherwise the polysilicon film is buried in the space and cannot be formed into a sidewall spacer shape by the etching back process. Thus, it is hard to miniaturize the semiconductor device because of the need to ensure the space.
The present invention has been achieved in view of the above drawbacks of the conventional devices. The present invention intends to provide a process for manufacturing a semiconductor memory device having floating gates and control gates, wherein an etching protecting film used at the formation of the control gate is formed in self-alignment with respect to a lower floating gate, and an upper floating gate is formed in self-alignment with respect to the etching protective film, thereby miniaturizing memory cells and facilitating the formation of the control gate.
The present invention provides a process for manufacturing a semiconductor memory device comprising the steps of: (a) forming a tunnel oxide film, a first conductive film to be a lower floating gate, a first insulating film and a second insulating film in this order on a semiconductor substrate and patterning the second insulating film, the first insulating film, the first conductive film and the tunnel oxide film into a desired configuration; (b) forming a third insulating film on the entire surface of the resulting semiconductor substrate; (c) reducing the third insulating film until the second insulating film is exposed; (d) removing the second insulating film; (e) removing the first insulating film while further reducing the third insulating film; (f) forming a second conductive film to be an upper floating gate on the first conductive film and the third insulating film; (g) flattening the second conductive film until the third insulating film is exposed; and (h) forming an interlayer capacitance film and a third conductive film to be a control gate on the second conductive film and the third insulating film, and patterning the third conductive film, the interlayer capacitance film, the second conductive film and the first conductive film to form a floating gate and the control gate.
Further, the present invention provides a semiconductor memory device comprising: a plurality of floating gates formed on a semiconductor substrate with intervention of a tunnel oxide film; an interlayer capacitance film formed on the floating gate; and a control gate formed on the interlayer insulating film, wherein the floating gate comprises a lower floating gate whose sidewalls are substantially vertical to the surface of the semiconductor substrate and an upper floating gate formed in a shape gradually widened towards its top on the lower floating gate, and an insulating film having lower sides substantially vertical to the surface of the semiconductor substrate and upper sides gradually narrowed towards its top in correspondence with the shape of the lower and upper floating gates.
These and other objects of the present application will become more readily apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.